By Gordon Roberts, Friedrich Taenzler, Mark Burns
With the proliferation of advanced semiconductor units containing electronic, analog, mixed-signal, and radio-frequency circuits, latest engineer needs to be fluent in all 4 circuit varieties. Written for complicated undergraduate and graduate-level scholars, in addition to engineering execs, An Introduction to Mixed-Signal IC attempt and Measurement, moment version, encompasses analog, mixed-signal and radio-frequency circuits assessments, with many appropriate business examples. The textual content assumes a superb historical past in analog and electronic circuits and a operating wisdom of desktops and desktop programming.
An creation to Mixed-Signal IC try out and Measurement, moment version, contains examples and illustrations--featuring state of the art commercial technology--to improve and brighten up the textual content. The ebook additionally introduces large-scale mixed-signal circuit and person circuit exams, discusses the value-added advantages of mixed-signal IC checking out to a manufacturer's product, and obviously defines the function of the attempt engineer.
New to This Edition
* a brand new bankruptcy on RF try out equipment and basics of RF Testing
* a brand new bankruptcy on Clock and Serial info Communications Channel Measurements
* insurance of RF load board design
* New insurance of probabilistic reasoning for mixed-signal trying out
Read or Download An Introduction to Mixed-Signal IC Test and Measurement PDF
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Additional resources for An Introduction to Mixed-Signal IC Test and Measurement
If the DUT output is between these thresholds, then the output state is considered a midpoint voltage. If it is outside these thresholds, then it is considered a valid logic level. Comparator results can also be ignored using a mask. Thus there are typically three drive states (HI, LO, and HIZ) and five compare states (HI, LO, and MID, VALID, and MASK). The usefulness of the valid comparison is not immediately obvious. If we want to test for valid VOH and VOL voltages from the output of a nondeterministic circuit such as an ADC, we cannot set the tester to expect HI or LO.
However, most ATE testers apply timing and formatting to the ones and zeros to create more complicated digital waveforms while minimizing the number of ones and zeros that must be stored in pattern memory. Timing and formatting is a type of data compression and decompression. The pattern data are formatted using the ATE tester’s formatter hardware, which is typically located inside the tester mainframe or on the pin card electronics in the test head. 7 shows how the pattern data are combined with timing and formatting information to create more complex waveforms.
Although much of the tester’s electronics are contained in the mainframe section, the test head contains the most sensitive measurement electronics. These circuits are the ones that require close proximity to the device under test. For example, high-speed digital signals benefit from short electrical paths between the tester’s digital drivers and the pins of the DUT. Therefore, the ATE tester’s digital drivers and receivers are located in the test head close to the DUT. A device interface board (DIB) forms the electrical interface between the ATE tester and the DUT.
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